Using assertions for wireless system monitoring and debugging

Debugging of embedded wireless systems is a challenge as the amount of information available from the nodes is limited. To enable system-level debugging of wireless networks, we have devised a distributed assertion support based on SystemVerilog Assertions (SVA). In this work, we have modeled wireless sensors at the transaction level in SystemVerilog. The proposed approach indicates that the assertions detect failure conditions along with a reduction in network traffic. This is due to embedding critical assertions within the sensor and eliminating the related trace messages. Experimental result shows 56% improvement in traffic.