Title :
Multigrain automatic parallelization in Japanese Millennium Project IT21. Advanced Parallelizing Compiler
Author :
Kasahara, Hironori ; Obata, Motoki ; Ishizaka, Kazuhisa ; Kimura, Keiji ; Kaminaga, Hiroki ; Nakano, Hirofumi ; Nagasawa, Kouhei ; Murai, Akiko ; Itagaki, Hiroki ; Shirako, Jun
Author_Institution :
Japanese Millennium Project IT21 Advancea Parallelizing Compiler, Waseda Univ., Tokyo, Japan
Abstract :
This paper describes OSCAR multigrain parallelizing compiler which has been developed in Japanese Millennium Project IT21 "Advanced Parallelizing Compiler" project and its performance on SMP machines. The compiler realizes multigrain parallelization for chip-multiprocessors to high-end servers. It hierarchically exploits coarse grain task parallelism among loops, subroutines and basic blocks and near fine grain parallelism among statements inside a basic block in addition to loop parallelism. Also, it globally optimizes cache use over different loops, or coarse grain tasks, based on the data localization technique to reduce memory access overhead. Current performance of OSCAR compiler for SPEC95fp is evaluated on different SMPs. For example, it gives us 3.7 times speedup for HYDRO2D, 1.8 times for SWIM, 1.7 times for SU2COR, 2.0 times for MGRID, 3.3 times for TURB3D on 8 processor IBM RS6000, against XL Fortran compiler ver 7.1 and 4.2 times speedup for SWIM and 2.2 times speedup for TURB3D on 4 processor Sun Ultra80 workstation against Forte6 update 2.
Keywords :
cache storage; parallel programming; parallelising compilers; program control structures; scheduling; shared memory systems; software performance evaluation; subroutines; Advanced Parallelizing Compiler; HYDRO2D; IBM RS6000; Japanese Millennium Project IT21; MGRID; OSCAR; SMP machines; SPEC95fp; SU2COR; SWIM; Sun Ultra80 workstation; TURB3D; XL Fortran compiler; cache use; chip-multiprocessors; coarse grain task parallelism; data localization technique; high-end servers; multigrain automatic parallelization; near fine grain parallelism; subroutines; Algorithms; Data analysis; Government; Memory architecture; Multiprocessing systems; Parallel processing; Program processors; Testing; Usability; Workstations;
Conference_Titel :
Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on
Print_ISBN :
0-7695-1730-7
DOI :
10.1109/PCEE.2002.1115213