DocumentCode :
2603698
Title :
Analysis and approach of TSV-based hierarchical power distribution networks for estimating 1st-Droop and resonant noise in 3DIC
Author :
Charles, Gary ; Franzon, Paul D. ; Kim, Jaemin ; Levin, Alex
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear :
2011
fDate :
23-26 Oct. 2011
Firstpage :
267
Lastpage :
270
Abstract :
In this paper, we model and analyse a hierarchical TSV-based chip-package co-design of the power delivery network (PDN) for three-dimensional integrated circuits (3DICs). It is a significant design consideration to combine chip/package PDN structures, accurately characterize and quantify their overall impedance,1st-droop effect and resonant noise behaviour for multi-stacked chips. To better understand how to reduce noise, particularly simultaneous switching noise (SSN) and determine voltage drop impact on power delivery networks for 3DICs, an analytical model is enhanced and applied to estimate the different noise levels of hierarchical TSV-based PDN structures. The on-chip parasitic capacitances and intentionally added decoupling capacitors help counter any Ldi/dt variations from the power supply rails as a result of the inductive effects in TSVs. With technology interest in embedded applications, the hierarchical chip-package TSV-based PDN design is modeled after a multi- stacked memory subsystem, a silicon interposer and package structure. A segmentation-based method is used to calculate the overall impedance of the hierarchical PDN system. An analytical expression is modified and used to quantify the transient response characteristics of 1st-droop and resonant noise property.
Keywords :
capacitors; chip scale packaging; integrated circuit noise; three-dimensional integrated circuits; 1st-droop effect; 3DIC; TSV-based PDN design; TSV-based hierarchical power distribution network; decoupling capacitor; hierarchical PDN system; hierarchical TSV-based PDN structure; hierarchical TSV-based chip-package codesign; hierarchical chip-package; multistacked chips; multistacked memory subsystem; noise level; noise reduction; on-chip parasitic capacitance; package structure; power delivery network; resonant noise behaviour; silicon interposer; simultaneous switching noise; three-dimensional integrated circuit; transient response; Analytical models; Impedance; Integrated circuit modeling; Mathematical model; Noise; Resonant frequency; Through-silicon vias; Through silicon vias (TSV); on-chip impedance and decoupling capacitance; power distribution networks (PDN); segmentation method;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
ISSN :
pending
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
Type :
conf
DOI :
10.1109/EPEPS.2011.6100243
Filename :
6100243
Link To Document :
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