Trade-offs between yield and reliability enhancement [VLSI]

Deep sub-micron VLSI technologies have led to a large increase in the number of devices per die as well as the switching speeds. These advances have been accompanied by increased design complexity and decreasing reliability. Scaling of the device dimensions has introduced “analog” effects on-chip that are causing signal integrity and delay problems. These problems are not easy to estimate and reduce after the VLSI layout has been finalized for fabrication and hence new CAD techniques are being proposed to tackle this problem up-front. Similarly, vastly increased manufacturing complexities have made manufacturing costs soar, and therefore chip yields need to be increased to cut losses due to manufacturing flaws. Extensive research has been done to suggest CAD solutions for reliability and yield enhancement, but these have treated the two as disjoint issues, and raised the thought-provoking question about their relationship. In this paper, we attempt to answer this question using crosstalk minimization and yield enhancement techniques, as applied to the VLSI layout as a case study. We study the trade-offs between yield and reliability enhancement by using a weighted average of both objectives as the cost function