Weighted-Tuple Synchronization for Parallel Architecture Simulators

Simulation is a critical tool for evaluating processor and program performance and behavior in newly proposed computer architectures. When modeling target machines with hundreds or thousands of cores, parallel simulation approaches are an increasingly popular method to reduce the long simulation times inherent in single-threaded simulation. Unfortunately, synchronization forces a tradeoffs between performance and fidelity in these parallel simulators. In this work, we study the link between synchronization violations and architectural metric error in the form of CPI error. Further, we introduce weighted-tuple synchronization, a new distributed synchronization scheme that improves error-delay for parallel simulation. Each core periodically selects a group of synchronization targets, forming a synchronization tuple. The lead core then waits for the other cores to catch up. Selection occurs randomly, but is weighted to favor cores which cause more synchronization violations. With weighted-tuple synchronization and a synchronization interval of 100 cycles, average error delay improves over barrier synchronization by 41% and over random-pair synchronization by 35%.