Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond

We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current /_Off down to 10 pA / mum at supply voltage V _DD = 1.2 V. NFET / PFET drive current I_DSAT = 550/250 muA /mum at /off = 100 pA/mum and gate length L_G ~ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre- amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.