Ultra-high density board technology for sub-100 μm pitch nano-wafer level packaging

As microsystems continue to move towards higher speed and microminiaturization, the demand for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2004 with <100 nm feature sizes, the area array I/O pitch will move towards 20-100 micron in the future. The 2002 ITRS Roadmap Update identifies the need to support sub-100 μm pitch flip-chip/WLP and data rates of 10Gbps in the package and board by the year 2010. The PRC and IME/NUS are developing 20-100 μm pitch interconnects as part of the A*STAR nano-WLP program. A critical part of this development involves board technology to simultaneously support wiring density to direct attach of these WLPs and high speed signals. The choice of base substrate and thin film dielectric is critical to meet the electrical performance targets and achieve reliable assembly of fine pitch WLPs. Modeling revealed that a low CTE substrate greatly enhances the reliability of all the interconnect solutions being pursued. The fabrication process was done on 300 mm × 300 mm and 300 mm × 450 mm panel sizes using state-of-the-art printed wiring board and microvia processes. Data rates of 5Gbps on board have been demonstrated for line lengths of 10 cm using A-PPE dielectric. Fine pitch routing using 20 μm lines and spaces on Hitachi E-679F low CTE laminate to support 200 μm pitch pads have been demonstrated. Initial substrates for 100 μm pitch have also been designed and fabricated.