Title :
A configurable CMOS multiplier/divider for analog VLSI
Author :
Ismail, M. ; Brannen, R. ; Takagi, S. ; Khan, R. ; Aaserud, O. ; Fujii, N. ; Khachab, N.
Author_Institution :
Dept. of Phys. Electron., Ohio State Univ., Columbus, OH, USA
Abstract :
The design of a simple CMOS operational-amplifier-based multiplier/divider is presented. The 2 operational amplifier and 6 MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuit in analog signal processing are discussed. The multiplier/divider circuit is insensitive to MOS intrinsic parasitic capacitances. It is sensitive to operational amplifier finite unity-gain bandwidth. This sensitivity may be mitigated using the configurability property of the circuit. Experimental results are provided to support some of the theoretical claims
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; dividing circuits; multiplying circuits; operational amplifiers; sensitivity analysis; MOSFET transistor circuit; analog VLSI; analog signal processing; configurable CMOS multiplier/divider; finite unity-gain bandwidth; four-quadrant division; four-quadrant multiplication; opamp based circuit; operational amplifier; sensitivity; Analog computers; Bandwidth; Biomedical signal processing; CMOS technology; Clocks; Impedance matching; MOSFET circuits; Parasitic capacitance; Very large scale integration; Voltage control;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393923
