Title :
SOA improvement of p-channel high-voltage SOI devices
Author :
Schwantes, Stefan ; Graf, Michael ; Dudek, Volker
Author_Institution :
Atmel Germany GmbH, Heilbronn, Germany
Abstract :
This paper presents a device structure for smart power SOI technologies. It is shown that the breakdown voltage BVDS and the safe operation area (SOA) of lateral p-channel DMOS transistors can be improved without degrading the on-resistance by locally optimizing the gate oxide thickness. Insight into the physical mechanisms taking place in lateral SOI DMOS transistors is presented. For the first time, the impact of the front gate potential on BVDS of p-channel SOI DMOS devices is discussed. The device structure is benchmarked by its performance and reliability.
Keywords :
power MOSFET; semiconductor device breakdown; semiconductor device reliability; silicon-on-insulator; BVDS breakdown voltage; device structure; gate oxide thickness optimization; high-voltage SOI devices; lateral SOI DMOS transistors; lateral p-channel DMOS transistors; safe operation area improvement; smart power SOI technology; Breakdown voltage; CMOS logic circuits; CMOS technology; Degradation; Electrodes; Impact ionization; Isolation technology; Logic devices; Semiconductor optical amplifiers; Switches;
Conference_Titel :
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN :
0-7803-9203-5
DOI :
10.1109/ESSDER.2005.1546629
