Electrical design for high data rate signals in conventional, BT based PBGA substrates using wire bonded interconnection

As data rates increase to 10 Giga-bits-per-second (10Gb/s) and above, it becomes increasingly difficult to provide electrically effective packaging solutions that remain economical. In many applications, a transition to flip chip interconnect and/or high cost substrate materials will result in a packaging solution that meets the performance requirements but has excessive cost. Despite concerns of electrical losses at high frequency in normal BT dielectric materials, it is possible to design standard PBGA packages that can support 10Gbps data rates using wire bond interconnection. By avoiding the use of more expensive dielectric materials and/or flip chip interconnection, the result can be the lowest cost packaging solution for these very high speed applications. In this work, an iterative process using high frequency electrical simulation has been used. This paper will detail several areas of focus: wire bonds, signal traces, via and ground plane structure, and solder ball bondpad structure. Each of these areas have been studied, simulated and optimized using Ansoft HFSS™. Design images and S-parameter graphs will be presented to show the electrical effect of the changes in each of these areas. The result of this work is an electrically optimized PBGA design with several pairs of wire bonded traces that are capable of transmitting signals at a data rate of 10Gb/s. Designs based on this work have entered production at these data rates.