• DocumentCode
    26092
  • Title

    Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks

  • Author

    Hanjoon Kim ; Yonggon Kim ; Kim, Jung-Ho

  • Author_Institution
    Dept. of Comput. Sci., KAIST, Daejeon, South Korea
  • Volume
    12
  • Issue
    2
  • fYear
    2013
  • fDate
    July-Dec. 2013
  • Firstpage
    47
  • Lastpage
    50
  • Abstract
    Bufferless on-chip networks are an alternative type of on-chip network organization that can improve the cost-efficiency of an on-chip network by removing router input buffers. However, bufferless on-chip network performance degrades at high load because of the increased network contention and large number of deflected packets. The energy benefit of bufferless network is also reduced because of the increased deflection. In this work, we propose a novel flow control for bufferless on-chip networks in high-throughput manycore accelerator architectures to reduce the impact of deflection routing. By using a clumsy flow control (CFC), instead of the per-hop flow control that is commonly used in buffered on-chip networks, we are able to reduce the amount of deflection by up to 92% on high-throughput workloads. As a result, on average, CFC can approximately match the performance of a baseline buffered router while reducing the energy consumption by approximately 39%.
  • Keywords
    computer architecture; microprocessor chips; network routing; network-on-chip; performance evaluation; CFC; bufferless NoC; clumsy flow control; cost-efficiency improvement; deflection routing impact reduction; energy benefit; energy consumption reduction; high-throughput bufferless on-chip networks; high-throughput manycore accelerator architectures; high-throughput workloads; network contention; on-chip network organization; router input buffer removal; Computer architecture; Data processing; Multiprocessing systems; Parallel architectures; System-on-chip; Computer Systems Organization; Interconnection architectures; Multiple Data Stream Architectures (Multiprocessors); On-chip interconnection networks; Parallel Architectures; Processor Architectures;
  • fLanguage
    English
  • Journal_Title
    Computer Architecture Letters
  • Publisher
    ieee
  • ISSN
    1556-6056
  • Type

    jour

  • DOI
    10.1109/L-CA.2012.22
  • Filename
    6246638