How to Prove that a Circuit is Fault-Free?

A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected part of the circuit. In case of passing of all the test groups, the circuit is proven fault-free. In case when not all test groups will pass, fault diagnosis by a sequential process of extending the fault-free core is possible.