• DocumentCode
    2610941
  • Title

    Improved impact-ionization modelling and validation with pn-junction diodes

  • Author

    Pan, Zhihao ; Holland, Steffen ; Schroeder, Dietmar ; Krautschneider, Wolfgang

  • Author_Institution
    NXP Semicond., Hamburg, Germany
  • fYear
    2010
  • fDate
    6-8 Sept. 2010
  • Firstpage
    287
  • Lastpage
    290
  • Abstract
    Impact-ionization at low and high electric field as well as the temperature dependence has to be modeled well in order to improve the predictive capability of TCAD tools. The high field behavior is of particular interest for ESD protection devices with low breakdown voltages which are used to protect ICs made with modern technologies. In this paper, the model for estimating the impact-ionization proposed by Valdinoci with the parameters of Reggiani has been examined with diodes of various breakdown voltages. It was found that the experimental breakdown voltages of the diodes are underestimated using that model. The cause was traced back to the overestimation of the electron impact-ionization coefficient at high electric fields. By adjusting the model parameters to the experiments of Van Overstraeten and Grant, who measured the impact-ionization coefficient in silicon for fields up to 7.7 × 105 V/cm, we extend the model´s validity to high fields. With the new parameter set, a much better agreement to the measured breakdown voltages is obtained. As a check for the temperature dependence of the impact-ionization, the diodes were further investigated under 100 ns transmission line pulses (TLP). The measured high-current I-V characteristic is well reproduced by simulations using the new model, as opposed to the well-established model based on Chynoweth´s law. Both the failure level and the damage location are well predicted by the simulation.
  • Keywords
    avalanche breakdown; avalanche diodes; electrostatic discharge; failure analysis; impact ionisation; p-i-n diodes; p-n junctions; semiconductor device breakdown; semiconductor device models; semiconductor process modelling; technology CAD (electronics); ESD protection devices; IC protection; TCAD predictive capability; breakdown voltage; damage location; electron impact-ionization coefficient; electrostatic discharge; failure level; high electric field behavior; high-current I-V characteristics; impact-ionization modelling; integrated circuit protection; model parameter set; pn-junction diodes; technology computer-aided design; temperature dependence; transmission line pulses; Current measurement; Electric fields; Electrostatic discharge; Silicon; Temperature measurement; Transmission line measurements; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on
  • Conference_Location
    Bologna
  • ISSN
    1946-1569
  • Print_ISBN
    978-1-4244-7701-2
  • Electronic_ISBN
    1946-1569
  • Type

    conf

  • DOI
    10.1109/SISPAD.2010.5604503
  • Filename
    5604503