Title :
Solving gate-matrix layout problems by simulated evolution
Author :
Hu, Yu Hen ; Mao, Chi-Yu
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
A simulated evolution algorithm for synthesizing CMOS random logic modules is presented. The gate-matrix layout problem is solved as a one-dimensional transistor gates placement problem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve the quality of the layout that is measured by the number of tracks needed for the given netlist. Extensive simulation results indicate that it produces very compact gate-matrix layouts
Keywords :
CMOS logic circuits; circuit layout CAD; logic CAD; logic design; logic gates; CMOS random logic modules; compact layouts; gate-matrix layout problems; layout quality; netlist; one-dimensional transistor gates placement; simulated evolution; Biological system modeling; CMOS logic circuits; Computational modeling; Evolution (biology); Iterative algorithms; Logic gates; Process design; Routing; Sun; Transistors;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394113
