Title :
A VLSI implementation of a cascade Viterbi decoder with traceback
Author :
Feygin, Gennady ; Chow, Paul ; Gulak, P. Glenn ; Chappel, John ; Goodes, Grant ; Hall, Oswin ; Sayes, Ahmad ; Singh, Satwant ; Smith, Michael B. ; Wilton, Steve
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto, Univ., Ont., Canada
Abstract :
A VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read pointer traceback technique. The overall design for a 16-state, rate 1/2-decoder requires about 26,000 transistors and a core area of 8.5 mm2 in a 1.2-μm two-level metal CMOS technology
Keywords :
CMOS digital integrated circuits; VLSI; Viterbi decoding; cascade networks; convolutional codes; error correction codes; 1.2 micron; VLSI implementation; Viterbi algorithm; cascade Viterbi decoder; core area; single read pointer traceback technique; survivor sequency memory management; traceback; two-level metal CMOS technology; CMOS technology; Computer architecture; Convolutional codes; Decoding; Memory management; Pipeline processing; Silicon; Throughput; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394131
