DocumentCode :
2611880
Title :
Architecture and VLSI design of a VLSI neural signal processor
Author :
Ramacher, U. ; Beichter, J. ; Bruls, N. ; Sicheneder, E.
Author_Institution :
Siemens AG Corp., Munich, Germany
fYear :
1993
fDate :
3-6 May 1993
Firstpage :
1975
Abstract :
A chip based on a scalable parallel systolic VLSI architecture has been designed for executing the compute-bound algorithmic primitives used by search and learning algorithms in neural networks and low level signal processing. The signal processor executes the algorithmic primitives and shared by all neural nets. The throughput is 800 million connection/s (1C = 16 bit) at 50 MHz. The chip contains 610 K transistors at 187 mm2 in a 1.0-μm CMOS technology. The I/O bandwidth for the weights is 3.2 Gbit/s and total data bandwidth is 10.9 Gbit/s. The processor is also useful for low-level signal preprocessing
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; integrated circuit design; learning (artificial intelligence); neural chips; systolic arrays; 1.0 micron; 3.2 Gbit/s; 50 MHz; CMOS technology.; I/O bandwidth; compute-bound algorithmic primitives; learning algorithms; low level signal processing; neural networks; scalable parallel systolic VLSI architecture; total data bandwidth; Algorithm design and analysis; Bandwidth; CMOS technology; Computer architecture; Computer networks; Neural networks; Signal design; Signal processing; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
Type :
conf
DOI :
10.1109/ISCAS.1993.394139
Filename :
394139
Link To Document :
بازگشت