Title :
A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch
Author :
Bellido, M.J. ; Valencia, M. ; Acosta, A.J. ; Barriga, A. ; Huertas, J.L. ; Dominguez-Castro, R.
Author_Institution :
Centro Nacional de Microelectronica, Sevilla, Spain
Abstract :
A new method is presented to calculate τ for CMOS latches, based on a single pole model. This method obtains very exact values of τ, at little expense of time, which in any case is much less than that of the methods reported. The dependence of τ on the latch geometry is analyzed
Keywords :
CMOS logic circuits; application specific integrated circuits; circuit analysis computing; circuit optimisation; flip-flops; logic CAD; CMOS latches; latch geometry; optimum latch; resolution coefficient; single pole model; Circuit simulation; Fabrication; Geometry; Latches; Logic; Metastasis; Process design; Routing; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394150
