Title :
Optimum gate voltage search for junctionless Tunnel FET using TCAD simulations
Author :
Vadivukkarasi, J. ; Kumar, N. Vinodh ; Nagarajan, K.K. ; Srinivasan, R.
Author_Institution :
ECE Dept., SSN Coll. of Eng., Chennai, India
Abstract :
The Structure of n type junctionless Tunnel FET is created and its characteristic is studied using TCAD simulations. The device simulations have been implemented with different voltage levels for different gate structures present in the device-gate over drain (VG1) and gate over source (VG2), and the transfer characteristics (ID-VG) are studied. Considering drive current (Ion)> off current (Ioff)> Ion/Ioff ratio, and subthreshold slope as metric, an optimum level of VG1 and VG2 is seen for the device.
Keywords :
field effect transistors; logic CAD; TCAD simulation; device-gate over drain; drive current; field effect transistors; gate over source; gate voltage search; junctionless tunnel FET; off current; transfer characteristics; transistor computer aided design; Educational institutions; Logic gates; MOSFET; Performance evaluation; Semiconductor process modeling; Tunneling; Band-to-Band Tunneling; Junctionless Tunnel FET; TCAD;
Conference_Titel :
Information Communication and Embedded Systems (ICICES), 2014 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4799-3835-3
DOI :
10.1109/ICICES.2014.7034121
