Title :
Whitespace redistribution for thermal via insertion in 3D stacked ICs
Author :
Wong, Eric ; Lim, Sung Kyu
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
Abstract :
One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding styles between device layers impose certain restrictions to where thermal vias may be inserted. This paper presents a whitespace redistribution algorithm that takes bonding style into consideration to improve thermal via placement, which in turn reduces temperature.
Keywords :
cooling; integrated circuit bonding; integrated circuit design; thermal management (packaging); 3D stacked IC design; bonding style; device layers impose certain restrictions; heat dissipation; whitespace redistribution; Bonding; Costs; Heat sinks; Integrated circuit interconnections; Performance analysis; Simulated annealing; Temperature distribution; Thermal factors; Tiles; Wire;
Conference_Titel :
Computer Design, 2007. ICCD 2007. 25th International Conference on
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
978-1-4244-1257-0
Electronic_ISBN :
1063-6404
DOI :
10.1109/ICCD.2007.4601912
