FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline

This paper presents a novel asynchronous pipeline based on two-phase handshake driven by an oscillation network embedded in each stage of the pipeline. The simplicity of the handshaking protocol stems from the requirement that all pipeline stages must have equal delay. This pipeline has been prototyped on a Xilinx Spartan FPGA to demonstrate the feasibility of asynchronous circuits on current FPGAs. Prototyping results show that this pipeline is highly suitable for coarse-grain logic