Title :
A new testable design of field programmable logic arrays
Author :
Rajsuman, R. ; Malaiya, Y.K. ; Jayasumana, A.P.
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A field programmable logic array (FPLA) design is presented which is easily testable. The programmable logic array (PLA) is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults, and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA
Keywords :
cellular arrays; logic arrays; logic design; logic testing; FPLA; bridging faults; field PLA; field programmable logic arrays; multiple faults; single crosspoint faults; stuck faults; testable design; universal test set; Circuit faults; Circuit testing; Costs; Delay; Fault detection; Fuses; Logic arrays; Logic design; Logic testing; Programmable logic arrays;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112072
