2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS

Network traffic speeds are increasing to meet the demands of data centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox transceiver is a significant portion of the optical module power. This paper demonstrates a low-power quad-lane 20-to-28Gb/s transceiver targeting 100GbE/40GbE (IEEE 802.3ba) standard. The transceiver features a low-jitter TX, half-rate calibrated RX slicer with folded active inductor and a wide-range PLL (20 to 28GHz) with low-power half-rate clock driver using programmable distributed inductors. It operates from a standard 0.9V supply and the power consumption for line-side transceiver is 780mW for 28Gb/s. Additionally the chipset integrates a system interface that is CAUI-compliant, composed of a 10-lane data bus operating at 9.95 to 11.2Gb/s. In default mode it converts 100GbE (10×10 Gb/s) signal to a 4×25Gb/s line signal and vice versa. The line-side interface can also be reconfigured as 40GbE, with both line- and system-side operating at 4×11.2Gb/s.