Title :
5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology
Author :
Yeung, A. ; Partovi, H. ; Harvard, Q. ; Ravezzi, L. ; Ngai, J. ; Homer, R. ; Ashcraft, M. ; Favor, G.
Author_Institution :
Appl. Micro, Sunnyvale, CA, USA
Abstract :
Potenza is a first generation 64b ARM v8 processor and memory sub-system of the X-GeneTM server platform [1]. The Potenza processor module (PMD) is an integrated design unit, comprising two identical cores sharing a 256KB L2 cache, and is designed to be scalable for different server configurations. Each PMD contains 84 million transistors, occupying over 14.8mm2, and averages 4.5W under representative workloads. The initial platform is configured with 4 PMDs, a shared 8MB L3 cache, and 4 DRAM channels arranged around a central switch. Potenza can operate up to 3GHz at 0.9V supply and is fabricated in a 40nm bulk CMOS technology using 10 metal layers (Fig. 5.8.7).
Keywords :
CMOS memory circuits; DRAM chips; cache storage; microprocessor chips; ARM v8 processor; DRAM channels; L2 cache; PMD; Potenza processor module; X-Gene server platform; bulk CMOS technology; central switch; frequency 3 GHz; integrated design unit; memory subsystem; metal layers; representative workloads; shared L3 cache; size 40 nm; storage capacity 64 bit; storage capacity 8 Kbit; storage capacity 8 Mbit; transistors; voltage 0.9 V; Arrays; CMOS integrated circuits; Clocks; Flip-flops; Program processors; Random access memory; Synchronization;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757360
