Title :
6.1 memory and system architecture for 400Gb/s networking and beyond
Author :
Maheshwari, Dinesh
Author_Institution :
Cypress Semicond., San Jose, CA, USA
Abstract :
Networking relies on fast line card packet rates that are directly proportional to and limited by the Random Transaction Rate (RTR) of the memory system. Networking line cards to date are ≤200Gb/s and were able to use memories optimized for latency (SRAM) and bandwidth (SDRAM) designed for computing systems. Next generation line cards are ≥400Gb/s and the memory system for these line cards need to be explicitly architected and designed for delivering the required high RTR.
Keywords :
DRAM chips; SRAM chips; memory architecture; SDRAM; SRAM; bit rate 400 Gbit/s; computing system; fast line card packet rates; memory architecture; networking line card; next generation line cards; random transaction rate; Application specific integrated circuits; Bandwidth; Memory management; Routing; SDRAM; Silicon;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757362
