DocumentCode :
2621084
Title :
The study of fault tolerant system design using complete evolution hardware
Author :
Subbiah, P. ; Ramamurthy, B.
Author_Institution :
Dept. of Electron. & Commun., JNTU Univ., Andhra Pradesh, India
Volume :
2
fYear :
2005
fDate :
25-27 July 2005
Firstpage :
642
Abstract :
Process engineering, process design and simulation, process supervision, control and estimation, process fault detection and diagnosis rely on the effective processing of unpredictable and imprecise information. A majority of applications require cooperation of two or more independently designed, separately located, but mutually affecting subsystems. In addition to good behavior of each of the subsystems, an effective coordination is very important to achieve the desired overall performance. Such a co-ordination can permit the use of commercially designed subsystems to perform more sophisticated tasks than at present and improve the operational reliability. However, such a co-ordination is very difficult to attain mainly due to the lack of precise system models and/or dynamic parameters. In such situations, the evolvable hardware (EHW) techniques, which can achieve the sophisticated level of information processing the brain is capable of, can excel. In this paper, a new multiple-sensor coordinator based sensor validation scheme combining the techniques of evolvable hardware and neural networks, is presented. The idea of this work is to develop a system that is resistant or tolerant to sensor failures (fault tolerance) by utilizing multiple sensor inputs connected to a programmable VLSI chip. The proposed system can be views as process modeling formalism and given the appropriate network topology; is capable of characterizing non linear functional relationships. The structure of the resulting evolvable hardware based process model can be considered generic, in the sense that little prior process knowledge is required. The knowledge about the plant dynamics and mapping characteristics are implicitly stored within the network. The proposed system help in extending the range of operation of the conventional control systems with respect to sensor validation at no extra (hardware) costs. The proposed design algorithms focus on using the characteristics that evolved systems present like, for example adaptation, auto-regulation and learning. The proposed sensor was tested for its effectiveness by introducing different sensor failures such as: sensor fails as open circuit, sensor fails as short circuit, multiple sensor failure etc. on a real time plant and in - each case the performance index was computed and found to be acceptable.
Keywords :
VLSI; fault tolerant computing; network topology; neural nets; sensor fusion; complete evolution hardware; control system; evolvable hardware based process model; fault tolerant system; information processing; multiple-sensor coordinator based sensor validation; network topology; neural network; nonlinear functional relationship; process design; process engineering; process fault detection; process fault diagnosis; process modeling formalism; process simulation; process supervision; programmable VLSI chip; sensor failures; Circuit testing; Design engineering; Fault detection; Fault diagnosis; Fault tolerant systems; Hardware; Process control; Process design; Sensor phenomena and characterization; Sensor systems; Evolvable hardware; Network Reconfiguration; Neural Network; Sensor validation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Granular Computing, 2005 IEEE International Conference on
Print_ISBN :
0-7803-9017-2
Type :
conf
DOI :
10.1109/GRC.2005.1547370
Filename :
1547370
Link To Document :
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