8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS

The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. For the implementation of high-density 10GBASE-T network switches, highly integrated transceivers are required that have both a small form factor and high power efficiency. This paper describes an analog front-end (AFE) that is used in a quad-port 10GBASE-T transceiver chip. The small form factor of the AFE allows for the use of a 23×23mm² BGA package, enabling implementation of 48-port switches with all transceivers in a single row on the PCB pitch-matched to the RJ45 connector arrays. The design achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR, and >60dBc receiver SFDR up to 400MHz. It occupies an area of 15.1mm² per port in a 40nm CMOS process. At 100m full 10Gb/s traffic, the AFE dissipates less than 1.75W.