• DocumentCode
    2623
  • Title

    Scaling Energy Per Operation via an Asynchronous Pipeline

  • Author

    Marr, B. ; Degnan, B. ; Hasler, P. ; Anderson, Dave

  • Author_Institution
    Raytheon Co., El Segundo, CA, USA
  • Volume
    21
  • Issue
    1
  • fYear
    2013
  • fDate
    Jan. 2013
  • Firstpage
    147
  • Lastpage
    151
  • Abstract
    Statistical analysis of computations per unit energy in processors over the last 30 years is given that illustrates a sharp reduction in the rate of energy efficiency improvements over the last several years resulting in the formation of an asymptotic “wall” with our dataset; we use the measure of giga multiply accumulates per Joule. We have developed an energy model which takes into account the realities of scaling, specifically for asynchronous systems. Studies of an energy efficient asynchronous pipeline show fabricated results of 17 Giga Operations per Joule in 0.6 μm at subthreshold when fully pipelined, and simulations at a more modern 65 nm process show a further order of magnitude improvement on that.
  • Keywords
    asynchronous circuits; low-power electronics; microprocessor chips; statistical analysis; asymptotic wall; asynchronous pipeline; energy efficiency improvement; energy scaling; processor; size 65 nm; statistical analysis; Adders; Delay; Logic gates; Pipelines; Program processors; Solid state circuits; Very large scale integration; Asynchronous circuits; digital integrated circuits; energy efficiency; integrated circuit modeling; performance analysis; power consumption;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2011.2178126
  • Filename
    6133317