Title :
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder
Author :
Tai-Chuan Ou ; Zhengya Zhang ; Papaefthymiou, Marios C.
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
This paper presents a 576b LDPC decoder test-chip designed using a charge-recovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operation by recovering charge from gate fanouts. When self-oscillating at 821MHz, the chip recovers 51.4% of the energy supplied to it. In terms of device count, this chip is more than an order of magnitude larger than the largest previously-reported chips with charge-recovery logic [3-4]. When operating at 821MHz, it achieves a 7.9Gb/s throughput at 7.3pJ/b/iteration, improving on results in [1-2,5] by at least 1.7× in energy efficiency and 2.3× in area efficiency.
Keywords :
CMOS logic circuits; codecs; integrated circuit manufacture; logic design; logic testing; parity check codes; CMOS; LDPC decoder test-chip designed; bit rate 7.9 Gbit/s; charge-recovery LDPC decoder; charge-recovery logic family; fabricated in a; frequency 821 MHz; inductors; size 65 nm; Clocks; Decoding; Inductors; Logic gates; Parity check codes; Resonant frequency; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757514
