DocumentCode
2625715
Title
Design of a PJM mode tag
Author
Jaehyuk, Youn ; Hoongee, Yang
Author_Institution
Dept. of Wireless Commun. Eng., Kwangwoon Univ., Seoul, South Korea
fYear
2012
fDate
15-17 Oct. 2012
Firstpage
992
Lastpage
993
Abstract
This paper presents a receiver structure for a PJM mode tag and its implementation results. To acquire the simplicity of a tag receiver, especially a synchronizer, some additional blocks other than correlators, such as initial time selector (ITS) and violation bit detector (VBD), are required. Performance is examined by simulation and its hardware is verified through a synthesized register transfer level (RTL) implementation.
Keywords
jitter; modulation; radio receivers; radiofrequency identification; PJM mode tag; additional blocks; initial time selector; phase jitter modulation; receiver structure; synchronizer; synthesized register transfer level; tag receiver; violation bit detector; Correlators; Demodulation; Detectors; Hardware; Payloads; Receivers; Synchronization; Bit synchronization; PJM mode; RFID; Violation bit;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications (APCC), 2012 18th Asia-Pacific Conference on
Conference_Location
Jeju Island
Print_ISBN
978-1-4673-4726-6
Electronic_ISBN
978-1-4673-4727-3
Type
conf
DOI
10.1109/APCC.2012.6388233
Filename
6388233
Link To Document