Title :
A 14-b 150 MS/s CMOS DAC with Digital Background Calibration
Author :
Chen, Hsin-Hung ; Lee, Jaesik ; Weiner, Joe ; Chen, Young-Kai ; Chen, Jiunn-Tsair
Author_Institution :
Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu
Abstract :
A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz and 67dB at 48.75MHz for sampling rate of 150MS/s. The DAC is implemented in a 0.35 mum CMOS process and active area is a 2.4times1.2 mm2
Keywords :
CMOS digital integrated circuits; calibration; digital-analogue conversion; 0.35 micron; 1.6 MHz; 48.75 MHz; CMOS DAC; CMOS process; current-steering DAC; digital background calibration; digital calibration; digital-to-analog converter; CMOS logic circuits; CMOS process; Calibration; Decoding; Digital-analog conversion; Dynamic range; Latches; Linearity; Switches; Switching circuits;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705307
