Yield and performance improvement through technology-design co-optimization in advanced technology nodes

As Si technology advances along with more complex fabrication process, new challenges arise during the advanced technology bring-up stage, especially due to convoluted interaction among process, device and circuit. New test structures and technology bring-up methodologies are necessary to account for process induced variation. Layout and circuit design need to be optimized to mitigate the process impact. This talk discusses these challenges and current approaches to address them.