Title :
The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor
Author :
Chang, Jonathan ; Huang, Ming ; Shoemaker, Jonathan ; Benoit, John ; Chen, Szu-Liang ; Chen, Wei ; Chiu, Siufu ; Ganesan, Raghuraman ; Leong, Gloria ; Lukka, Venkata ; Rusu, Stefan ; Srivastava, Durgesh
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
The 16-way set associative, single-ported 16MB cache for the dual-core Xeonreg processor uses a 0.624mum2 cell in a 65nm 8-metal technology. Only 0.8% of the cache is powered up for an access. Sleep transistors are used in the SRAM array and peripherals. Dynamic Pellston with a history buffer protects the cache from latent defects and infant mortality failures
Keywords :
SRAM chips; buffer circuits; cache storage; content-addressable storage; microprocessor chips; multi-threading; 16 MByte; 65 nm; SRAM; Xeon processor; dual core processor; dynamic Pellston; history buffer; infant mortality failures; latent defects; multithreaded processor; on-die L3 cache; sleep transistors; Copper; Data buses; Decoding; History; Land surface temperature; MOS devices; Protection; Random access memory; Sleep; Temperature control;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705342
