Static gate power consumption model based on power contributors

Accurate and fast estimation of the static power consumption in various design corners for nanoscale integrated circuits is a very important task since it facilitates power and noise analysis procedures. The power contributor approach which is based on the separability of the power components can be used for this purpose. In this paper, parametric models for the power contributor currents are produced for the cells of an industry oriented library. Using these models, the power contributor method is evaluated for the estimation of the total static power consumption of the library cells. The models produced are expressed as a function of the power supply voltage, temperature and the transistor width. Results show that the proposed model estimations present an average error of about 0.4% while the maximum error remains less than 2% for all the design corners of the tested cells.