The Design and Implementation of AMBA Interfaced High-Performance SDRAM Controller for HDTV SoC

For cost reasons, the usage of SDRAM is preferred in HDTV SoC. However, accessing SDRAM is a complex task, especially when the same SDRAM is shared by various functional modules with different bandwidth requirements and requirements for responding speeds. For two-way cable networked HDTV SoC especially when the network data throughput is very high, the performance of SDRAM controller is very important. This paper describes a high-performance AMBA interfaced SDRAM controller design that exploits SDRAM features and uses popular IC designing techniques such as the buffering technology, pingponging between buffers and adopts bank-closing control as well. Simulation results under a realistic application demonstrate a significant decrease of total execution time of the program used in our experiments. The SDRAM controller IP is suitable for FPGA implementation and is flexible enough to be used in the application of two-way cable networked HDTV SoC.