• DocumentCode
    263186
  • Title

    FPGA implemented cut-through vs store-and-forward switches for reliable ethernet networks

  • Author

    Astarloa, Armando ; Lazaro, Jesus ; Bidarte, Unai ; Araujo, Jose Angel ; Moreira, Naiara

  • Author_Institution
    Fac. of Eng., Univ. of the Basque Country, Bilbao, Spain
  • fYear
    2014
  • fDate
    26-28 Nov. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper, the latency times offered by two COTS IEC 62439-3 switch IP cores implementable on FPGAs have been compared. The first one, combines Cut-Through with Store-and-Forward switching architectures. The second IP is based only on Store-and-Forward switching technique. The analysis shows that a custom architecture that combines Cut-Through with Store-and-Forward approaches and takes advantage from Reconfigurable Technology offers the best latency times under any circumstance. This parameter is critical for the applications and sectors addressed in these new Reliable Ethernet protocols. Additionally, both IPs have been compared attending other features and resources required for their implementation. This comparison shows that a specifically designed architecture for the protocols specified in IEC 62439-3 offers excellent latency time and requires less resources than traditional Store-and-Forward ones.
  • Keywords
    computer network reliability; field programmable gate arrays; local area networks; protocols; COTS IEC 62439-3 switch IP cores; FPGA; reliable ethernet networks; reliable ethernet protocols; store-and-forward switches; store-and-forward switching architectures; store-and-forward switching technique; Field programmable gate arrays; IEC standards; IP networks; Ports (Computers); Protocols; Switches; FPGA; High-availability Seamless Redundancy (HSR); IEC 61850; IEC 62439; IEC 62439-3-5; Parallel Redundancy Protocol (PRP); Realtime Ethernet; Reliable Ethernet; cut-through;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on
  • Conference_Location
    Madrid
  • Type

    conf

  • DOI
    10.1109/DCIS.2014.7035561
  • Filename
    7035561