Fast hardware-in-the-loop verification platform: A case study for convolutional decoders

The time required for system analysis and verification has invariably become the bottleneck of the development process as designs become more complex. Methodologies involving configurable hardware have proven to be the only ones to break the inverse relationship between accuracy in simulation and performance in verification. In this work we present a Hardware-in-the-Loop based platform that substantially reduces the time required for system verification and parameter fine tuning. The verification platform has been used to evaluate the performance of the physical layer of a WLAN 802.11a compliant transceiver. Compared to a software RTL simulation this platform reduces simulation time by a factor of at least 10³.