A 1 MHz compact digitally controlled perceptron integrated circuit implementation with process insensitivity

Author

Pino, José L. ; Sculley, Terry L. ; Brooke, Martin A.

Author_Institution

Sch. of Electr. Eng., George Inst. of Technol., Atlanta, GA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

1066

Abstract

A fast, compact process and temperature insensitive perceptron neural network is introduced. The integrated circuit proposed forms one layer in a perceptron neural network that can be easily cascaded to form a multiple-layer network. The implementation realizes practical 8-bit two´s complement digital weights. The perceptron implementation presented holds promise in that it has a highly predictable output independent of process parameters and thermal effects

Keywords

CMOS integrated circuits; amplifiers; artificial intelligence; neural nets; 1 MHz; 8 bit; compact process; digitally controlled perceptron integrated circuit; easily cascaded; highly predictable output; multiple-layer network; perceptron implementation; perceptron neural network; process insensitivity; temperature insensitive perceptron neural network; Digital control; Digital integrated circuits; Image recognition; Integrated circuit technology; Mirrors; Neural networks; Pattern recognition; Piecewise linear techniques; Telephony; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112293

Filename

112293