Storage Architecture for an On-chip Multi-core Processor

Modern multi-core processor architectures strive for the highest possible performance of various applications. This paper discusses a triple-based multi-core architecture which supports object-oriented methodology and applications in hardware level. However, the Memory Wall is still the bottleneck which should be resolved to decrease the disparity between how fast a CPU can operate on data and how fast it can get data. We present hierarchical shared memory system architecture (HSM) which is hierarchically constructed memory shared by multi-cores. Moreover, we propose a new approach mapping data among different levels of cache and memory, which is called partially-inclusive cache mapping policy that facilitates the coherence of shared memory. This paper focus on object-oriented systems combined with the HSM and partially-inclusive policy and presents a new objects management model. The analysis based on comparisons between our objects management and link structured object organization methods shows that our method is predominant in spatial and temporal aspects on memory parallel access efficiency and costs less storage space to organize objects.