Simulation and modeling of hot carrier degradation of cascoded NMOS transistors for power management applications

Author

Varghese, D. ; Mathur, G. ; Reddy, V. ; Heater, J. ; Krishnan, S.

Author_Institution

Analog Technol. Dev., Texas Instrum., Dallas, TX, USA

fYear

2012

fDate

15-19 April 2012

Abstract

We use a lateral scaling methodology based on the bond-dispersion model to develop a generalized hot carrier degradation model for cascoded NMOS transistors in power management applications. Spatial profiling of interface traps (N_IT) based on charge pumping measurements is used to identify damage regions responsible for V_T and I_DLIN degradation and to explain their time dependencies.

Keywords

MOSFET; charge pump circuits; circuit simulation; hot carriers; integrated circuit modelling; low-power electronics; bond-dispersion model; cascoded NMOS transistor; charge pumping measurement; damage region identification; generalized hot carrier degradation model; hot carrier degradation modeling; hot carrier degradation simulation; interface trap; lateral scaling methodology; power management application; spatial profiling; time dependency; Charge pumps; Degradation; Electric fields; Hot carriers; Logic gates; Stress; Transistors; Bond-dispersion model; Cascoded Transistors; Hot Carrier Degradation; Lifetime Model;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2012 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4577-1678-2

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2012.6241807

Filename

6241807