• DocumentCode
    2634411
  • Title

    NMOS-inside 6T SRAM layout reducing neutron-induced multiple cell upsets

  • Author

    Yoshimoto, Shusuke ; Amashita, Takuro ; Okumura, Shunsuke ; Nii, Koji ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

  • fYear
    2012
  • fDate
    15-19 April 2012
  • Abstract
    This paper presents a novel NMOS-inside 6T SRAM cell layout that reduces a neutron-induced MCU SER on a same wordline. We implemented a 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-inside 6T SRAM cells.
  • Keywords
    CMOS integrated circuits; SRAM chips; CMOS process; MCU SER; NMOS-inside 6T; SRAM layout; neutron-accelerated test; neutron-induced multiple cell upsets; Layout; MOS devices; Neutrons; Radiation effects; Random access memory; Semiconductor device measurement; Transistors; SRAM; multiple cell upset (MCU); neutron particle; soft error rate (SER); triple well; twin well;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium (IRPS), 2012 IEEE International
  • Conference_Location
    Anaheim, CA
  • ISSN
    1541-7026
  • Print_ISBN
    978-1-4577-1678-2
  • Electronic_ISBN
    1541-7026
  • Type

    conf

  • DOI
    10.1109/IRPS.2012.6241847
  • Filename
    6241847
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2634411