• DocumentCode
    2634857
  • Title

    Session Abstract

  • fYear
    2007
  • fDate
    39203
  • Firstpage
    287
  • Lastpage
    287
  • Abstract
    Today¿s wafer manufacturing facilities generate large amounts of electrical test and process data. Traditionally this data has been collected, stored and analyzed to identify sources of yield loss and continually provide real-time characterization of the manufacturing process itself. In-line inspections, parametric tests and CD, film thickness and metal overlay measurements occur at numerous points during wafer processing. This data is analyzed correlated and displayed in many forms including charts, tables and wafer/die maps. Ultimately, these capabilities lead to the identification and capture of an abnormality on the wafer with an FA imaging tool.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2007. 25th IEEE
  • Conference_Location
    Berkeley, CA, USA
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-2812-0
  • Type

    conf

  • DOI
    10.1109/VTS.2007.64
  • Filename
    4209926