DocumentCode :
2635001
Title :
Fault simulation and test generation for clock delay faults
Author :
Higami, Yoshinobu ; Takahashi, Hiroshi ; Kobayashi, Shin-ya ; Saluja, Kewal K.
Author_Institution :
Grad. Sch. of Sci. & Eng., Ehime Univ., Matsuyama, Japan
fYear :
2011
fDate :
25-28 Jan. 2011
Firstpage :
799
Lastpage :
805
Abstract :
In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.
Keywords :
clocks; fault simulation; flip-flops; logic testing; clock delay faults; fault simulation; flip-flops; launch-on-capture test strategy; test generation; Automatic test pattern generation; Circuit faults; Clocks; Computational modeling; Delay; Logic gates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4244-7515-5
Type :
conf
DOI :
10.1109/ASPDAC.2011.5722299
Filename :
5722299
Link To Document :
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