DocumentCode :
2635032
Title :
Backend dielectric chip reliability simulator for complex interconnect geometries
Author :
Chen, Chang-Chih ; Bashir, Muhammad ; Milor, Linda ; Kim, Dae Hyun ; Lim, Sung Kyu
Author_Institution :
Sch. of Electr. & Comptuer Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2012
fDate :
15-19 April 2012
Abstract :
Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown. Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.
Keywords :
circuit reliability; electric breakdown; backend dielectric breakdown; backend dielectric chip reliability simulator; chip lifetime; circuit reliability; complex interconnect geometry; failure rate; parallel track; width effect; Dielectric breakdown; Dielectrics; Equations; Geometry; Layout; Mathematical model; Reliability; TDDB; chip lifetime; dielectric breakdown; irregular interconnect geometries; reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1541-7026
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
Type :
conf
DOI :
10.1109/IRPS.2012.6241878
Filename :
6241878
Link To Document :
بازگشت