Title :
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles
Author :
Furuta, J. ; Hamanaka, C. ; Kobayashi, K. ; Onodera, H.
Author_Institution :
Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
Abstract :
We fabricated a 65nm LSI including flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. It consists of two FF arrays as follows. One is an array composed of redundant FFs to confirm radiation hardness of the proposed and conventional redundant FFs. The other is an array composed of conventional D-FFs to measure SEU (Single Event Upset) and MCU(Multiple Cell Upset) by the distance from tap cells.
Keywords :
alpha-particle effects; flip-flops; large scale integration; neutron effects; FF arrays; LSI; MCU; SEU; conventional D-FF; conventional redundant FF; flip-flop array; high-energy alpha particles; high-energy neutron particles; multiple cell upset; radiation hardness; single event upset; size 65 nm; soft error resiliency; Alpha particles; Arrays; Clocks; Latches; Radiation effects; Shift registers; Single event upset;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7515-5
DOI :
10.1109/ASPDAC.2011.5722306
