Network-on-Chip Architecture Exploration Framework

In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The automated generation of Network-on-Chip architectures covers beside the generation of the communication infrastructure, the automated integration of IP-components. The automated integration of IP-components is based on IP-XACT interface descriptions of these components. In this paper, we show the integration of components into the Network-on-Chip architecture exemplarily for the SimpleScalar Instruction-Set-Simulator (ISS). The Network-on-Chip architecture used in this paper, is based on a parametrizable switch implemented as Transaction-Level-Model (TLM) in SystemC. The Transaction-Level-Model of the switch provides the possibility of integrating different routing algorithms like deterministic or adaptive routing algorithms. Different Network-on-Chip architectures like mesh-, torus-, and hypercube-topologies can be generated, based on this switch. The proposed framework can be used for exploration and optimization of Network-on-Chip architectures, by comparing Network-on-Chip architectures with different topologies and routing algorithms.