Title :
Verticalization Of Direct Structural Table In Synthesis Of Mealy FSMS For FPGAs
Author :
Bukowiec, A. ; Barkalov, A.
Author_Institution :
Zielona Univ., Gora
Abstract :
The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal possible number of bits. In this case only one decoder is used for implementation of the microoperations system. This method permits to minimize a number of outputs of the combinational part of Mealy FSM in comparison with the same characteristic of Mealy FSM with encoding of fields of compatible microoperations
Keywords :
field programmable gate arrays; finite state machines; logic circuits; logic design; Mealy outputs; direct structural table; field programmable gate arrays; finite state machine; logic circuit; logic synthesis; microoperations system; Automata; Circuit synthesis; Decoding; Digital systems; Field programmable gate arrays; Logic circuits; Logic devices; Programmable logic arrays; Switches; Table lookup;
Conference_Titel :
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location :
Gdynia
Print_ISBN :
83-922632-2-7
DOI :
10.1109/MIXDES.2006.1706609