DocumentCode
2641407
Title
SDR implementation of a DVB-T2 transmitter: The core building blocks
Author
FANTOZZI, Carlo ; Vangelista, Lorenzo ; Vogrig, Daniele ; CAMPANA, Ottavio
fYear
2011
fDate
9-12 Jan. 2011
Firstpage
391
Lastpage
392
Abstract
In this paper we describe the implementation of a DVB-T2 transmitter on a commercially-available hardware platform. The implementation leverages on the Software-Defined Radio (SDR) characteristics of the platform to attain on-the fly reconfigurability. The paper focuses on the two most computationally intensive blocks of the transmitter: the LDPC encoder and the IFFT processor.
Keywords
digital video broadcasting; fast Fourier transforms; parity check codes; software radio; DVB-T2 transmitter; IFFT processor; LDPC encoder; SDR implementation; commercially-available hardware platform; core building blocks; inverse fast Fourier transform; second-generation digital terrestrial transmission system; software-defined radio; Digital video broadcasting; Encoding; Field programmable gate arrays; Modulation; Parity check codes; Radio transmitters; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4244-8711-0
Type
conf
DOI
10.1109/ICCE.2011.5722644
Filename
5722644
Link To Document