DocumentCode :
2641518
Title :
An efficient methodology for transaction-level design of multi-core h.264 video decoder
Author :
Xia, Bingbing ; Qiao, Fei ; Yang, Huazhong ; Wang, Hui
Author_Institution :
Tsinghua Nat. Lab. for Inf. & Technol., Tsinghua Univ., Beijing, China
fYear :
2011
fDate :
9-12 Jan. 2011
Firstpage :
399
Lastpage :
400
Abstract :
H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate the performance of such application-specific multi-core systems effectively, a method based on the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is given, and experiments show that it can effectively simulate the system in a short time and more importantly, it can be used to help analyze the efficiency of each task-parallelization strategy. After optimization, the speedup ratio for each slice decoding can get about 3.06 on average under 4-core multi-core systems.
Keywords :
C language; code standards; embedded systems; multi-threading; shared memory systems; transaction processing; video coding; H.264; MPEG2; TLM language; embedded instruments; multi-core system; multi-thread parallelization; parallel programming; shared-memory model; transaction-level design; video decoder; Analytical models; Decoding; Design methodology; Multicore processing; Parallel programming; Time domain analysis; Time varying systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location :
Las Vegas, NV
ISSN :
2158-3994
Print_ISBN :
978-1-4244-8711-0
Type :
conf
DOI :
10.1109/ICCE.2011.5722648
Filename :
5722648
Link To Document :
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