A harmonic-rejection mixer with improved design algorithm for broadband TV tuners

A wide-band harmonic rejection mixer for TV tuners with an improved design algorithm is fabricated in 65-nm CMOS process. A more realistic mathematical formula is derived to calculate harmonic rejection performance. The third and fifth order harmonic rejection ratio calculation, based on the new proposed equations, precisely predicts simulation results. A systematic design optimization technique pushes the mean of the harmonic rejection performance to a higher value resulting in better yield. The measured third and fifth order harmonic rejection ratio for 2000 samples is better than -56dBc for VHFI and II bands without increasing any circuit complexity or implementation difficulty.