Title :
A built-in self-testing approach for minimizing hardware overhead
Author :
Chiu, Scott S K ; Papachristou, Christos A.
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques
Keywords :
automatic testing; built-in self test; integrated circuit testing; area overhead; built-in self-test; built-in self-testing; circuit structure; hardware insertion technique; minimizing hardware overhead; module functionality; register transfer level designs; system level BIST; test hardware overhead; Built-in self-test; Circuit testing; Costs; Delay; Hardware; Logic; Pattern analysis; Registers; System testing; Test equipment;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139898
